Linux Synchronization
We need mechanisms for synchronization when two or more threads simultaneously access a shared resource. By using synchronization mechanisms of the kernel only allows one thread to wait during the execution of other threads.
Competition in the processor systems
One might think that, how many threads can run simultaneously, if a single processor. In a single processor system, even though multiple threads can not operate simultaneously, but one thread can be displaced by an interrupt, or it can be descheduled run at a different thread on the CPU. Preemption may raise competition concerns even data loss, etc. Result barring an interruption masking is a simple technique used on single processor systems to solve problems associated with competition. If a global variable is both an interrupt handler and a kernel thread, the interrupts are masked, the wire during the read shared / update the shared variable.
Competition on SMP systems
On an SMP system are two or more processors on a single shared main memory. Several threads can run simultaneously on different processors, and can access data simultaneously on the main memory. Here is masking interrupts on a single processor or all processors solve the problem is not that we are still running talks on other processors. We need more complex mechanisms by which we will discuss later.
Problems with simultaneous access to shared resources
It is very important to understand the problems or side effects caused by simultaneous access to a resource from multiple threads. Let us understand this with a simple example.
Suppose there is a global variable called “state” (8 bits wide). Consider two threads where one thread wants to define a number of bits, while thread 2 wants the number two state bits of the shared variable. If a bit is already set, they must stay together.
To set a bit, a processor must be followed by three operations
1) Read to register the current value of the internal in his memory.
2) Set the bit in the register.
3) Keep to register the change in value in the memory.
In fact, the common steps to the read-modify-write must be performed. Let the initial value of global variable “state” is 0xF0 (11110000b). The final value after the execution of two son should 0xF3 (11110011b). However, this is not the case. It may happen that the final value of the “state” is either 0xF1 or 0xF2 or 0xF3. This can occur when both run simultaneously son. See the following example.
1) First, a wire-load value (0xF0), the global variable “state” in its registry.
2) Then, two wire-load value (0xF0), the global variable “state” in its registration. (Since only one processor to access memory at a time to accept that a thread loads the first value, the thread-2)
3) Thread-1 Number of bits set to 1, in its register (0xF0 -> 0xF1). Thread-2 also defines two number of bits in the register (0xF0 -> 0xF2) (two processors to do the same because they use their internal registers.)
4) About one-saves the current value (0xF1) in its register memory.
5) Then thread 2 saves the value (0xF2) in its register memory
(Suppose a new thread first stores)
This is the final value 0xF2 0xF3 it should have been. We lost a number of bits set by a thread.
If the thread-2 have their first stored value, the final value 0xF1. have been lost in this case, bit by thread-2 would be. May result in access to competitive data corruption.
How to solve the above problem
The above problem can be solved only if all three operations can be prevented in one step (all other processors to access the shared variable performed while the CPU is a read-modify-write to him.)
For this we need the support of the process equipment. Most modern processors provide instructions to perform the above operations atomic.
Take an example of a 80386
80 386 contains an instruction “SLL”, a little reminder. The format is as follows: memaddr SLL, bitnum / / This will set memaddr bitnum
But there is no guarantee that the above operation is atomic. To solve this problem is a mechanism 80 386, the memory bus can be blocked until the read-modify-write instruction has completed execution. This will precede the instruction opcode of “lock” done. If the controller detects the lock code, it locks the memory bus is completed by the investigation. No other processor accessing the memory bus until the investigation is complete blocked design.
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